Evolution of embedded system design methods

I. Background of changes in embedded system design methods The evolution of embedded system design methods is generally due to the traction of application requirements and the promotion of IT technology. 

1. With the continuous innovation and development of microelectronics technology, the integration and processing level of large-scale integrated circuits continue to increase. The combination of silicon materials and human intelligence has produced a large number of low-cost, high-reliability and high-precision microelectronic structural modules, driving a new technological field and industry development. The device programmable ideas and micro-processing technology developed on this basis can be used to change and implement hardware functions in software. The large number of applications of microprocessors and various programmable large-scale integrated dedicated circuits and semi-custom devices has created a new world of applications, and has been widely influenced and gradually changed the social activities of human production, life and learning. 

2, the performance of the computer hardware platform has been greatly improved, so that many complex algorithms and convenient interfaces can be realized, which greatly improves the work efficiency and provides a physical basis for the complex design of complex embedded systems. 

3, high-performance EDA integrated development tools (platforms) have been greatly developed, and its automation and intelligence are constantly improving, providing different uses and different levels of editing, layout, routing, compilation, and synthesis for complex embedded system design. Integrated, easy-to-learn and easy-to-use development integration environment for simulation, testing, verification, and device programming. 

4. The development of hardware description language HDL (Hardware DescrIPtion Language) provides a working medium for building various hardware models for complex electronic system design. Its descriptive power and abstraction capabilities have brought about major changes in hardware circuits, especially semi-custom large-scale integrated circuit designs. At present, Verilog HDL, which has become IEEE's STD1076 standard VHDL, IEEE STD 1364 standard, and Altera's enterprise standard AHDL, etc., have been used.

Due to the development and standardization of HDL, there have been a number of companies in the world that use HDL to design professional IC modules. Its task is to use HDL to describe the function and structure of integrated circuits according to common or special functions, and to form different levels of IP core modules through different levels of verification for chip designers to assemble or integrate.

The IP (Intellectual Property) kernel module is a pre-designed or even verified integrated circuit, device or component with certain deterministic functions. It comes in several different forms. The IP core module has different levels of behavior, structure, and physical design, corresponding to the "soft IP core" that mainly describes the functional behavior, and the "solid IP" that describes the structure. The firmware (firm IP core) and the physical description and process-proven "hard IP core" (hard IP core) three levels. This is equivalent to the design techniques of blanks, semi-finished products and finished products of integrated circuits (devices or components).

Soft IP cores are usually submitted to users with some kind of HDL text. It has been designed for behavioral level optimization and functional verification, but it does not contain any specific physical information. According to this, the user can synthesize the correct gate-level netlist and can carry out subsequent structural design, which has the greatest flexibility and can be easily integrated with other external logic circuits by means of EDA synthesis tools, according to various The semiconductor process is designed to have devices with different properties. The total number of gates of a general IP circuit that can be commercialized is more than 5000 gates. However, if the subsequent design is not appropriate, it may cause the entire result to fail. Soft IP cores are also known as virtual devices.

The hard IP core is based on the physical design of a semiconductor process. It has a fixed topology and a specific process, and has been verified by the process to have guaranteed performance. The form that is provided to the user is a circuit physical structure mask layout and a full set of process files, which is a complete set of technologies that can be used.

The design depth of the solid IP core is between the soft IP core and the hard IP core. In addition to completing all the design of the hard IP core, it also completes the design steps of gate level synthesis and timing simulation. It is generally submitted to the user in the form of a gate-level netlist.

TI, Philips and Atmel are authorized by Intel to use their MCS\|51 IP core module to develop their own unique MCS\|51 compatible MCU.

Commonly used IP core modules have different CPUs (32/64-bit CISC/RISC-structured CPU or 8/16-bit microcontroller/microcontroller, such as 8051, etc.), 32/64-bit DSP (such as 320C30), DRAM, SRAM, EEPROM, Flashmemory, A/D, D/A, MPEG/JPEG, USB, PCI, standard interfaces, network elements, compilers, encoder/decoders, and analog device modules. The rich IP core module library provides a basic guarantee for the rapid design of ASICs and monolithic systems and the rapid occupation of the market.

5, the advancement of software technology, especially the introduction of the embedded real-time operating system EOS (Embedded Operation System), provides a low-level support and high-efficiency development platform for the development of complex embedded system applications. EOS is a powerful, widely used real-time multitasking system software. It generally has various system resource management functions that the operating system has, and the user can call the function form through the application program interface API to implement various resource management. User programs can be developed and run on the basis of EOS. Compared with the OS in the general-purpose system machine, it mainly has the characteristics of short and fine system kernel, low overhead, strong real-time performance and high reliability. The well-established EOS also provides drivers for a variety of devices. In order to adapt to network applications and Internet applications. TCP/IP protocol support is also available. The current popular EOS includes 3Com's Palm OS, Microsoft's Windows CE and Windows NT Embedded 4.0, Tokyo University's Tron and various open source embedded Linux, and the domestically developed Kais Group's Hopen OS and HBOS of Zhejiang University.

Second, the changes in embedded system design methods [Page]

Programmers who used to be good at software design generally "respected" hardware circuit design. Hardware design and software design were considered to be completely different technologies. With the development of electronic information technology, designers born out of electronic engineering often step into software programming. The main form is to learn the corresponding assembly language programming through the application of a microcontroller (known in domestic practice as a single-chip microcomputer). When designing a larger distributed control system, it is necessary to use the popular PC as the upper machine, so as to further learn to use the high-level language programming such as Quick BASIC, C, C++, VC and VB as the system program. The system interface forms a centralized distributed control system by multi-machine communication with the front-end machine controlled by the single-chip microcomputer.

Designers born out of software programming are seldom interested in learning application circuit design. However, with the rapid development of computer technology, especially the invention of hardware description language HDL, the system hardware design method has changed. The hardware composition and behavior of digital system can be described and simulated by HDL. In this case, the design hardware circuit is no longer a patent of the hardware design engineer. The designers who are good at software programming can use HDL tools to describe the behavior, function, structure, data flow, signal connection relationship and timing relationship of the hardware circuit. Design a hardware system that meets various requirements.

The EDA tool allows for two design input tools that accommodate the needs of both hardware circuit designers and software programmers. Let designers with hardware backgrounds use the schematic input method that they are used to, and let designers with software backgrounds use hardware description language input methods. Since the input is made with the HDL description, it is closer to the system behavior description, and is more convenient for synthesis, time domain transfer and modification, and can also create a process-independent design file. Therefore, those who are good at software programming once master the HDL and some necessary The hardware knowledge can often design better hardware circuits and systems than engineers accustomed to traditional design. Therefore, engineers accustomed to traditional design should learn to use HDL to describe and program.

Third, the three levels of embedded system design

Embedded system design has three different levels.

1. Design method with PCB CAD software and ICE as the main tools

This is the method that has been used by designers of MCU application systems in the past until now. The steps are abstracted and then concrete. The abstract design is mainly based on the functional requirements to be realized by the embedded application system. The system functions are refined, divided into several functional modules, the system functional block diagram is drawn, and the functional modules are assigned hardware and software functions.

Specific designs include hardware design and software design. The hardware design mainly selects and combines the components required for each functional module according to the performance parameter requirements. The basic principle of selection is the most cost-effective general-purpose component that can be purchased in the market. If necessary, it is necessary to conduct separate tests, functional tests and performance tests on the unsure parts, and find a relatively optimized solution from the module to the system, and draw the circuit schematic. A key step in hardware design is the layout and routing of system components using printed circuit board (PCB) computer-aided design (CAD) software, followed by printed board processing, assembly, and hardware debugging.

The biggest part of the workload is software design. Software design runs through the entire system design process, including task analysis, resource allocation, module partitioning, process design and refinement, and code debugging. The software design workload is mainly focused on program debugging, so the software debugging tool is the key. The most common and effective tool is the In-Circuit Emulator (ICE).

2. Design method using EDA tool software and EOS as development platform

With the development of microelectronics process technology, various general-purpose programmable semi-custom logic devices have emerged. In hardware design, designers can use these semi-custom devices to gradually make a number of standard logic devices that were originally interconnected through printed circuit board circuits into an application-specific integrated circuit (ASIC), thus laying out the printed circuit board layout and The complexity of routing translates into the complexity of configuration within a semi-custom device. However, the design of semi-custom devices does not require designers to have knowledge and experience in semiconductor process and on-chip integrated circuit layout and routing. As semi-custom devices become larger and larger, more and more devices can be integrated, making wiring, assembly, and debugging of interconnected devices on the board less and less, not only greatly reducing the area of ​​the printed board. The number of connectors and the number of connectors reduces the overall system cost, increases the flexibility of the programmable application, and more importantly reduces the system power consumption, improves the system operating speed, and greatly improves the reliability and security of the system.

In this way, hardware designers have chosen and used standard versatile integrated circuit devices from the past, gradually turning to their own design and production of some specialized integrated circuit devices, which are supported by various EDA tool software.

Semi-custom logic devices have evolved through programmable logic array PLA, programmable array logic PAL, general purpose array logic GAL, complex programmable logic device CPLD, and field programmable gate array FPGA. The trend is increasing integration and speed, increasing functionality, more versatile structure, and more flexible and convenient use.

Designers can design and build user-specific LSIs using a variety of EDA tools and standard CPLDs and FPGAs. Then, through the bottom-up design method, the integrated circuit, programmable peripheral device, selected ASIC and embedded microprocessor or microcontroller with semi-custom device design are laid out and wired on the printed circuit board to form a system. .

3. Design method based on IP core library and using software and hardware collaborative design technology

After the 1990s, the transition from "integrated circuit" level design to "integrated system" level design began. It has entered the design phase of the system on a chIP (SOC) and has entered the practical stage. This design method is not simply to re-integrate all the integrated circuits required by the system into one chip. If this is achieved in a single-chip system, it is impossible to achieve the high density, high speed and high required by the single-chip system. Performance, small size, low voltage, low power consumption and other indicators, especially low power requirements. The design of the monolithic system should proceed from the performance requirements of the whole system, and closely combine the microprocessor, model algorithm, chip structure, peripheral circuit circuit and device design, and realize the synergy between the system software and hardware based on the new concept. Designed to perform the functions of the entire system on a single chip. Sometimes it is possible to make the system on several chips. Because, in fact, not all systems can be implemented on a single chip; it is also possible that the cost of implementing a single-chip system is too high to lose commercial value. At present, the practical single-chip system is also a simple single-chip system, such as a smart IC card. But several well-known semiconductor manufacturers are in the process of developing and developing complex monolithic systems like single-chip PCs.

The design of a monolithic system is neither realistic nor necessary if it starts from scratch. Because in addition to the immature design, time-tested, the system performance and quality are not guaranteed, and the commercial value is lost because the design cycle is too long.

In order to speed up the single-chip system design cycle and improve the reliability of the system, one of the most effective ways is to use the mature and optimized IP core module for design integration and secondary development through authorization, using glue logic technology GLT (Glue Logic Technology) ), embed these IP core modules into the SOC. The IP core module is the basis for a single-chip system design. Which level of IP core module to purchase depends on the existing base, time, funds, and other conditions. Buying a hard IP core module is the least risky, but the biggest payout is inevitable. But in general, the purchase of IP core modules can not only reduce development risks, but also save development costs, because the cost of purchasing IP core modules is generally lower than the cost of their own design and verification. Of course, not all of the required IP core modules are commercially available. In order to monopolize the market, some key IP core modules developed by some companies (at least temporarily) are unwilling to authorize the transfer. IP core modules like this have to organize themselves to develop.

Each of these three levels has its own range of applications. From an application development perspective, the first two methods have been used for quite some time. The third level of design methodology can only be used to design a simple monolithic system for a typical application. The complex monolithic system can be designed and implemented by some large semiconductor manufacturers, and the single-chip system realized by this method can only be invested in the widely used and scaled application systems. There are also applications, because technical issues or business value issues are not suitable for monolithic implementation. When they launch the corresponding single-chip system in the form of a product, the application personnel can simply select it. Therefore, the three levels of design methods will coexist and will not simply replace the former with the latter. The primary application designer will focus on the first method; the experienced designer will focus on the second method; a very professional designer will use the third method to design and apply a simple single-chip system. However, all designers can apply a dedicated monolithic system designed by the semiconductor manufacturer using the third method.

Conclusion [Page]

At present, the design of the three levels in China is in the state of “face”, “line” and “point”. Electronic information system designers who are accustomed to the first-level design method need to gradually transition to the second level; the second level design method should be gradually developed from “line” to “face”; the third level design method needs the relevant national departments to IT development strategy and planning, organization of various aspects of research and coordinated development. The third level of design method should be gradually developed from “point” to “line”.

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